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| - 1 - k4b1g0446e k4b1g0846e K4B1G1646E rev. 1.4, nov. 2009 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2009 samsung electronics co., ltd. all rights reserved. datasheet 1gb e-die ddr3 sdram 60fbga & 84fbga with lead-free & halogen-free (rohs compliant)
- 2 - datasheet ddr3 sdram rev. 1.4 K4B1G1646E k4b1g0846e k4b1g0446e revision history revision no. history draft date remark editor 1.0 - first release feb. 2009 - s.h.kim 1.01 - corrected typo. june. 2009 - s.h.kim 1.1 - add iddq2nt, iddq4r, idd8 specification july. 2009 - s.h.kim 1.2 - corrected ac timing table sep. 2009 - s.h.kim 1.3 - added idd current specification for ddr3-1600 oct. 2009 - s.h.kim 1.4 - added layout and corrected typo. nov. 2009 - s.h.kim - 3 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e table of contents 1gb e-die ddr3 sdram 1. ordering information ........................................................................................................ ............................................. 5 2. key features............................................................................................................... ................................................. 5 3. package pinout/mechanical dimension & addressing........ .............. .............. .............. .............. ............ ...................... 6 3.1 x4 package pinout (top view) : 78ball fbga package .............. .............. ........... ........... ........... ............ ................. 6 3.2 x8 package pinout (top view) : 78ball fbga package .............. .............. ........... ........... ........... ............ ................. 7 3.3 x16 package pinout (top view) : 96ball fbga package . .............. .............. ........... ........... ........... .......... ................ 8 3.4 fbga package dimension (x4/x8)............................................................................................. ............................. 9 3.5 fbga package dimension (x16)............................................................................................... .............................. 10 4. input/output functional description........................................................................................ ..................................... 11 5. ddr3 sdram addressing . .............. .............. .............. .............. .............. ........... ............ ......... .................................... 12 6. absolute maximum rati ngs .................................................................................................... ...................................... 13 6.1 absolute maximum dc ratings... ............................................................................................. ............................... 13 6.2 dram component operating temperature range ................................................................................. ............... 13 7. ac & dc operating conditions................................................................................................ ..................................... 13 7.1 recommended dc operating conditions (sstl_1.5)........ ..................................................................... ................ 13 8. ac & dc input measurement levels ............................................................................................ ................................ 14 8.1 ac & dc logic input levels for single-ended signal s ............... .............. ........... ........... ............ ......... ...................... 14 8.2 v ref tolerances.................................................................................................................... .................................. 15 8.3 ac & dc logic input levels for differential signal s ............. .............. ........... ............ ........... .......... ........................ 16 8.3.1. differential signals definiti on .............. .............. .............. .............. ........... ............ .......... ................................... 16 8.3.2. differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) .................................................. 16 8.3.3. single-ended requirements for differential sign als ............... .............. .............. .............. ............. ..................... 17 8.4 differential input cross point voltage................. .................................................................... ................................. 18 8.5 slew rate definition for differ ential input signals ..... .............. .............. .............. .............. ........... ............................. 18 8.6 slew rate definitions for differential input signal s .............. .............. ............ ........... ........... ......... ............................ 18 9. ac & dc output measurement levels ................ .......................................................................... .............................. 19 9.1 single-ended ac & dc output levels......................................................................................... ............................ 19 9.2 differential ac & dc output levels......................................................................................... ................................ 19 9.3 single-ended output slew rate .............................................................................................. ................................ 19 9.4 differential output slew rate .............................................................................................. .................................... 20 9.5 reference load for ac timing and output slew rate ............. .............. .............. ........... ........... ........... .................. 20 9.6 overshoot/undershoot specificat ion ......................................................................................... .............................. 21 9.6.1. address and control overshoot and undershoot specifications........... .............. .............. ........... ........... ......... 21 9.6.2. clock, data, strobe and mask overshoot and undersh oot specifications .............. .............. .............. .......... .. 21 9.7 34ohm output driver dc electrical characteristics. .............. .............. ........... ............ ........... ........... ....................... 22 9.7.1. output drive temperature and voltage sensitivity ........................................................................ .................. 23 9.8 on-die termination (odt) levels and i-v characterist ics .................................................................... ................. 23 9.8.1. odt dc electrical characteristics ................ ....................................................................... ............................ 24 9.8.2. odt temperature and voltage sensitivity ................................................................................ ...................... 25 9.9 odt timing definition s ..................................................................................................... ...................................... 26 9.9.1. test load for odt timings............................................................................................... ............................... 26 9.9.2. odt timing definitions .................................................................................................. .................................. 26 10. idd current measure method ................................................................................................. .................................... 29 10.1 idd measurement conditions ................................................................................................ ............................... 29 11. 1gb ddr3 sdram e-die idd specification table .............................................................................. ..................... 38 12. input/output capacitance ................................................................................................... ........................................ 40 13. electrical characteristics and ac timing for ddr3- 800 to ddr3-1600 ........ .............. .............. ........... .......... ............. 41 13.1 clock specification ....................................................................................................... ......................................... 41 13.1.1. definition for tc k(avg)................................................................................................ .................................... 41 13.1.2. definition for tck(abs)... ............................................................................................. .................................... 41 13.1.3. definition fo r tch(avg) and tcl(avg)................................................................................... ........................... 41 13.1.4. definition for note for tjit( per), tjit(per, ick) ...................................................................... ........................... 41 13.1.5. definition for tjit (cc), tjit(cc, ick) ................................................................................. ................................ 41 13.1.6. definition for terr(nper). ............................................................................................. .................................. 41 13.2 refresh parameters by device density42 - 4 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 13.3 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ........ .............. .............. ............ .......... ....... 42 13.3.1. speed bin table notes ...... ............................................................................................ ................................ 45 14. timing parameters by speed grade ..................... ...................................................................... ............................... 46 14.1 jitter notes .............................................................................................................. .............................................. 49 14.2 timing parameter notes............ ........................................................................................ .................................... 50 14.3 address/command setup, hold and derating : ....... ......................................................................... .................... 51 14.4 data setup, hold and slew rate derating : ..... ............................................................................ ......................... 57 - 5 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 1.0 ordering information [ table 1 ] samsung 1gb ddr3 e-die ordering information table note : 1. speed bin is in order of cl-trcd-trp. 2.0 key features [ table 2 ] 1gb ddr3 e-die speed bins organization ddr3-800 (6-6-6) ddr3-1066 (7-7-7) ddr3-1333 (9-9-9) ddr3-1600 (11-11-11) package 256mx4 k4b1g0446e-hcf7 k4b1g0446e-hcf8 k 4b1g0446e-hch9 k4b1g0446e-hck0 78 fbga 128mx8 k4b1g0846e-hcf7 k4b1g0846e-hcf8 k 4b1g0846e-hch9 k4b1g0846e-hck0 78 fbga 64mx16 K4B1G1646E-hcf7 K4B1G1646E-hcf8 k 4b1g1646e-hch9 K4B1G1646E-hck0 96 fbga speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit 6-6-6 7-7-7 9-9-9 11-11-11 tck(min) 2.5 1.875 1.5 1.25 ns cas latency 6 7 9 11 nck trcd(min) 15 13.125 13.5 13.75 ns trp(min) 15 13.125 13.5 13.75 ns tras(min) 37.5 37.5 36 35 ns trc(min) 52.5 50.625 49.5 48.75 ns ? jedec standard 1.5v 0.075v power supply ?v ddq = 1.5v 0.075v ? 400 mhz f ck for 800mb/sec/pin, 533mhz f ck for 1066mb/sec/pin, 667mhz f ck for 1333mb/sec/pin, 800mhz f ck for 1600mb/sec/pin ? 8 banks ? posted cas ? programmable cas latency(posted cas): 6, 7, 8, 9, 10, 11 ? programmable additive latency: 0, cl-2 or cl-1 clock ? programmable cas write latency (cwl) = 5 (ddr3-800), 6 (ddr3-1066), 7 (ddr3-1333) and 8 (ddr3-1600) ? 8-bit pre-fetch ? burst length: 8 (interleave without any limit, sequential with starting address ?000? only), 4 with tccd = 4 which does not allow seamless read or write [either on the fly using a12 or mrs] ? bi-directional differential data-strobe ? internal(self) calibration : intern al self calibration through zq pin (rzq : 240 ohm 1%) ? on die termination using odt pin ? average refresh period 7.8us at lower than t case 85 c, 3.9us at 85 c < t case < 95 c ? asynchronous reset ? package : 78 balls fbga - x4/x8 96 balls fbga - x16 ? all of lead-free products are compliant for rohs ? all of products are halogen-free the 1gb ddr3 sdram e-die is organized as a 32mbit x 4 i/os x 8banks, 16mbit x 8 i/os x 8banks or 8mbit x 16 i/os x 8 banks devic e. this synchro- nous device achieves high speed double-data-rate transfer rates of up to 1600mb/sec/pin (ddr3-1600) for general applications. the chip is designed to comply with the following key ddr3 sdram fea- tures such as posted cas, programmable cwl, internal (self) calibration, on die termination using odt pin and asynchronous reset . all of the control and address inputs are synchronized with a pair of exter- nally supplied differential clocks. inputs are latched at the crosspoint of dif- ferential clocks (ck rising and ck falling). all i/os are synchronized with a pair of bidirectional strobes (dqs and dqs ) in a source synchronous fash- ion. the address bus is used to c onvey row, column, and bank address information in a ras /cas multiplexing style. the ddr3 device operates with a single 1.5v 0.075v power supply and 1.5v 0.075v v ddq . the 1gb ddr3 e-die device is ava ilable in 78ball fbgas(x4/x8) and 96ball fbga(x16) note : the functionality described and the timing specifications included in this data sheet are for the dll enabled mode of operation. note : this data sheet is an abstract of full ddr3 specificati on and does not cover the common features which are described in ?ddr 3 sdram device operation & timing diagram?. - 6 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 3.0 package pinout/mechanical dimension & addressing 3.1 x4 package pinout (top view) : 78ball fbga package 1 2 3 4 5 6 7 8 9 a v ss v dd nc nc v ss v dd a b v ss v ssq dq0 dm v ssq v ddq b c v ddq dq2 dqs dq1 dq3 v ssq c d v ssq nc dqs v dd v ss v ssq d e v refdq v ddq nc nc nc v ddq e f nc v ss ras ck v ss nc f g odt v dd cas ck v dd cke g h nc cs we a10/ap zq nc h j v ss ba0 ba2 nc v refca v ss j k v dd a3 a0 a12/bc ba1 v dd k l v ss a5 a2 a1 a4 v ss l m v dd a7 a9 a11 a6 v dd m n v ss reset a13 nc a8 v ss n populated ball ball not populated ball locations (x4) top view (see the balls through the package) 1234 89 567 a b c d e f g h j k l n m - 7 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 3.2 x8 package pinout (top vi ew) : 78ball fbga package 1 2 3 4 5 6 7 8 9 a v ss v dd nc nu/tdos v ss v dd a b v ss v ssq dq0 dm/tdqs v ssq v ddq b c v ddq dq2 dqs dq1 dq3 v ssq c d v ssq dq6 dqs v dd v ss v ssq d e v refdq v ddq dq4 dq7 dq5 v ddq e f nc v ss ras ck v ss nc f g odt v dd cas ck v dd cke g h nc cs we a10/ap zq nc h j v ss ba0 ba2 nc v refca v ss j k v dd a3 a0 a12/bc ba1 v dd k l v ss a5 a2 a1 a4 v ss l m v dd a7 a9 a11 a6 v dd m n v ss reset a13 nc a8 v ss n ball locations (x8) populated ball ball not populated top view (see the balls through the package) 1234 89 567 a b c d e f g h j k l n m - 8 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 3.3 x16 package pinout (top view) : 96ball fbga package 1 2 3 4 5 6 7 8 9 a v ddq dqu5 dqu7 dqu4 v ddq v ss a b v ssq v dd v ss dqsu dqu6 v ssq b c v ddq dqu3 dqu1 dqsu dqu2 v ddq c d v ssq v ddq dmu dqu0 v ssq v dd d e v ss v ssq dql0 dml v ssq v ddq e f v ddq dql2 dqsl dql1 dql3 v ssq f g v ssq dql6 dqsl v dd v ss v ssq g h v refdq v ddq dql4 dql7 dql5 v ddq h j nc v ss ras ck v ss nc j k odt v dd cas ck v dd cke k l nc cs we a10/ap zq nc l m v ss ba0 ba2 nc v refca v ss m n v dd a3 a0 a12/bc ba1 v dd n p v ss a5 a2 a1 a4 v ss p r v dd a7 a9 a11 a6 v dd r t v ss reset nc nc a8 v ss t populated ball ball not populated ball locations (x16) top view (see the balls through the package) 1234 89 567 a b c d e f g h j k l n m p r t - 9 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 3.4 fbga package dimension (x4/x8) a b c d e f g h m n 7.50 0.10 0.80 x 12 = 9.60 3.20 0.80 4.80 78 - ? 0.45 solder ball 0.2 ab m (datum b) (datum a) 0.10max 1.10 0.10 #a1 1.60 7.50 0.10 11.00 0.10 molding area 0.35 0.05 #a1 index mark b a bottom view top view 11.00 0.10 j k l 0.80 0.80 (post reflow ? 0.50 0.05) (0.95) (1.90) units : millimeters 87654321 9 - 10 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 3.5 fbga package dimension (x16) a b c d e f g h j l m n p r t 7.50 0.10 3.20 0.80 6.00 (datum b) (datum a) 0.10max 1.10 0.10 #a1 1.60 7.50 0.10 13.30 0.10 0.35 0.05 #a1 index mark top view 13.30 0.10 k 0.80 x 15 = 12.00 b a 0.80 0.40 96 - ? 0.45 solder ball 0.2 ab m molding area (post reflow ? 0.50 0.05) (0.95) (1.90) bottom view units : millimeters 8 7654321 97 - 11 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 4.0 input/output functional description [ table 3 ] input/output function description symbol type function ck, ck input clock: ck and ck are differential clock inputs. all address and c ontrol input signals are sampled on the crossing of the positive edge of ck and negative edge of ck . output (read) data is referenced to the crossings of ck and ck cke input clock enable: cke high activates, and cke low deactivates, in ternal clock signals and dev ice input buffers and output drivers. taking cke low provides precharge power- down and self refresh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for self refresh exit. after v refca has become stable during the power on and initialization sequence, it mu st be maintained during all operations (including self- refresh). cke must be maintained high throughout read and write accesses. input buffers, excluding ck, ck , odt and cke are disabled during power-down. input buffers , excluding cke, are disabled during self -refresh. cs input chip select: all commands are masked when cs is registered high. cs provides for external rank selection on systems with multiple ranks. cs is considered part of the command code. odt input on die termination: odt (registered high) enables termination resi stance internal to the ddr3 sdram. when enabled, odt is only applied to each dq, dqs, dqs and dm/tdqs, nu/tdqs (when tdqs is enabled via mode register a11=1 in mr1) signal for x8 configurations. t he odt pin will be ignored if the mode register (mr1) is pro- grammed to disable odt. ras , cas , we input command inputs: ras , cas and we (along with cs ) define the command being entered. dm (dmu), (dml) input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high coinci- dent with that input data during a write access. dm is sa mpled on both edges of dqs. for x8 device, the function of dm or tdqs/tdqs is enabled by mode register a11 setting in mr1. ba0 - ba2 input bank address inputs: ba0 - ba2 define to which bank an active, read, write or precharge command is being applied. bank address also determines if the mode regist er or extended mode register is to be accessed during a mrs cycle. a0 - a13 input address inputs: provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (a10/ap and a12/bc have additional functions, see below) the address inputs also provide the op-code during mode register set commands. a10 / ap input autoprecharge: a10 is sampled during read/write commands to determine whether autoprecharge should be per- formed to the accessed bank after the read/write operat ion. (high:autoprecharge; low: no autoprecharge) a10 is sampled during a precharge command to determine w hether the precharge applies to one bank (a10 low) or all banks (a10 high). if only one bank is to be pr echarged, the bank is selected by bank addresses. a12 / bc input burst chop: a12 is sampled during read and write commands to det ermine if burst chop(on-the-fly) will be per- formed. (high : no burst chop, low : burst chopped). see command truth table for details reset input active low asynchronous reset: reset is active when reset is low, and inactive when reset is high. reset must be high during normal operation. reset is a cmos rail to rail signal with dc high and low at 80% and 20% of v dd , i.e. 1.20v for dc high and 0.30v for dc low. dq input/output data input/ output: bi-directional data bus. dqs, (dqs ) input/output data strobe: output with read data, input with write data. edge-aligned with read data, centered in write data. for the x16, dqsl: corresponds to the data on dql0-dql7; dqsu corresponds to the data on dqu0-dqu7. the data strobe dqs, dqsl and dqsu are paired with differential signals dqs , dqsl and dqsu, respectively, to provide dif- ferential pair signaling to the system during reads and wr ites. ddr3 sdram supports differential data strobe only and does not support single-ended. tdqs, (tdqs )output termination data strobe: tdqs/tdqs is applicable for x8 drams only. when enabled via mode register a11=1 in mr1, dram will enable the same termi nation resistance function on tdqs/tdqs that is applied to dqs/dqs . when disabled via mode register a11=0 in mr1, dm/tdq s will provide the data mask function and tdqs is not used. x4/ x16 drams must disable the tdqs func tion via mode register a11=0 in mr1. nc no connect: no internal electrical connection is present. v ddq supply dq power supply: 1.5v +/- 0.075v v ssq supply dq ground v dd supply power supply: 1.5v +/- 0.075v v ss supply ground v refdq supply reference voltage for dq v refca supply reference voltage for ca zq supply reference pin for zq calibration note : input only pins (ba0-ba2, a0-a13, ras , cas , we , cs , cke, odt and reset ) do not supply termination. - 12 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 5. ddr3 sdram addressing 1gb 2gb 4gb 8gb note 1 : page size is the number of bytes of data deliv ered from the array to the internal sense amplifiers when an active command is registered. page size is per bank, calculated as follows: page size = 2 colbits * org 8 where, colbits = the number of column address bits, org = the number of i/o (dq) bits configuration 256mb x 4 128mb x 8 64mb x 16 # of bank 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 13 a 0 - a 13 a 0 - a 12 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size *1 1 kb 1 kb 2 kb configuration 512mb x 4 256mb x 8 128mb x 16 # of bank 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 14 a 0 - a 14 a 0 - a 13 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size *1 1 kb 1 kb 2 kb configuration 1gb x 4 512mb x 8 256mb x 16 # of bank 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 15 a 0 - a 15 a 0 - a 14 column address a 0 - a 9, a 11 a 0 - a 9 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size *1 1 kb 1 kb 2 kb configuration 2gb x 4 1gb x 8 512mb x 16 # of bank 8 8 8 bank address ba0 - ba2 ba0 - ba2 ba0 - ba2 auto precharge a 10 /ap a 10 /ap a 10 /ap row address a 0 - a 15 a 0 - a 15 a 0 - a 15 column address a 0 - a 9, a 11, a 13 a 0 - a 9, a 11 a 0 - a 9 bc switch on the fly a 12 /bc a 12 /bc a 12 /bc page size *1 2 kb 2 kb 2 kb - 13 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 6. absolute maximum ratings 6.1 absolute maximum dc ratings [ table 4 ] absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum rating s? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the ce nter/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 3. v dd and v ddq must be within 300mv of each other at all times;and v ref must be not greater than 0.6 x v ddq , when v dd and v ddq are less than 500mv; v ref may be equal to or less than 300mv. 6.2 dram component operating temperature range [ table 5 ] temperature range note : 1. operating temperature t oper is the case surface temperature on the center/top side of the dram. for measurement conditions, please refer to the jedec docu ment jesd51-2. 2. the normal temperature range specifies the temperatures wher e all dram specifications will be supported. during operation, t he dram case temperature must be main - tained between 0-85 c under all operating conditions 3. some applications require operation of the extended temperature range between 85 c and 95 c case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore redu cing the refresh interval trefi to 3.9us. it is also possible to specify a component with 1x refresh (trefi to 7.8us) in the extended temperature range. b) if self-refresh operation is required in the extended temperat ure range, then it is mandatory to either use the manual self- refresh mode with extended temperature range capability (mr2 a6 = 0 b and mr2 a7 = 1 b ) or enable the optional auto self-refresh mode (mr2 a6 = 1 b and mr2 a7 = 0 b ) 7. ac & dc operating conditions 7.1 recommended dc operating conditions (sstl_1.5) [ table 6 ] recommended dc operating conditions note : 1. under all conditions v ddq must be less than or equal to v dd . 2. v ddq tracks with v dd . ac parameters are measured with v dd and v ddq tied together. symbol parameter rating units note v dd voltage on v dd pin relative to vss -0.4 v ~ 1.975 v v 1,3 v ddq voltage on v ddq pin relative to vss -0.4 v ~ 1.975 v v 1,3 v in, v out voltage on any pin relative to vss -0.4 v ~ 1.975 v v 1 t stg storage temperature -55 to +100 c 1, 2 symbol parameter rating unit note t oper operating temperature range 0 to 95 c 1, 2, 3 symbol parameter rating units note min. typ. max. v dd supply voltage 1.425 1.5 1.575 v 1,2 v ddq supply voltage for output 1.425 1.5 1.575 v 1,2 - 14 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 8. ac & dc input measurement levels 8.1 ac & dc logic input leve ls for single-ended signals [ table 7 ] single-ended ac & dc input levels for command and address note : 1. for input only pins except reset , v ref = v refca (dc) 2. see ?overshoot/undershoot specification? on page 21. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref (dc) by more than 1% v dd (for reference : approx. 15mv) 4. for reference : approx. v dd /2 15mv [ table 8 ] single-ended ac & dc input levels for dq and dm note : 1. for input only pins except reset , v ref = v refdq (dc) 2. see ?overshoot/undershoot specification? on page 21. 3. the ac peak noise on v ref may not allow v ref to deviate from v ref (dc) by more than 1% v dd (for reference : approx. 15mv) 4. for reference : approx. v dd /2 15mv 5. single ended swing requirement for dqs - dqs is 350mv (peak to peak). differential swing requirement for dqs - dqs is 700mv (peak to peak). symbol parameter ddr3-800/1066 ddr3-1333/1600 unit note min. max. min. max. v ih.ca (dc) dc input logic high v ref + 100 v dd v ref + 100 v dd mv 1 v il.ca (dc) dc input logic low v ss v ref - 100 v ss v ref - 100 mv 1 v ih.ca (ac) ac input logic high v ref + 175 - v ref + 175 -mv1,2 v il.ca (ac) ac input logic low - v ref - 175 - v ref - 175 mv 1,2 v ih.ca (ac150) ac input logic high - - v ref +150 -mv1,2 v il.ca (ac150) ac input logic lowm - - - v ref -150 mv 1,2 v refca (dc) reference voltage for add, cmd inputs 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd v3,4 symbol parameter ddr3-800/1066 ddr3-1333/1600 unit note min. max. min. max. v ih.dq (dc100) dc input logic high v ref + 100 v dd v ref + 100 v dd mv 1 v il.dq (dc100) dc input logic low v ss v ref - 100 v ss v ref - 100 mv 1 v ih.dq (ac175) ac input logic high v ref + 175 - v ref + 150 - mv 1,2,5 v il.dq (ac175) ac input logic low - v ref - 175 - v ref - 150 mv 1,2,5 v ih.dq (ac150) ac input logic high v ref + 150 note 2 - - mv 1,2,5 v il.dq (ac150) ac input logic low note 2 v ref - 150 --mv1,2,5 v ref dq (dc) reference voltage for dq, dm inputs 0.49*v dd 0.51*v dd 0.49*v dd 0.51*v dd v3,4 - 15 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 8.2 v ref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages v refca and v refdq are illustrate in figure 1. it shows a valid reference voltage v ref (t) as a function of time. (v ref stands for v refca and v refdq likewise). v ref (dc) is the linear average of v ref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirement in table 7 on page 14. furthermore v ref (t) may temporarily deviate from v ref (dc) by no more than 1% v dd . figure 1. illustration of v ref (dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurements v ih (ac), v ih (dc), v il (ac) and v il (dc) are dependent on v ref . "v ref " shall be understood as v ref (dc), as defined in figure 1 . this clarifies, that dc-variations of v ref affect the absolute voltage a signal has to reach to achi eve a valid high or low level and therefore the time to which setup and hold is measured. system ti ming and voltage budgets need to account for v ref (dc) deviations from the optimum position within the data-eye of the input signals. this also clarifies that the dram setup/hold specificatio n and derating values need to include time and voltage associated wit h v ref ac-noise. timing and voltage effects due to ac-noise on v ref up to the specified limit (+/-1% of v dd ) are included in dram timings and their associated deratings. voltage v dd v ss time - 16 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 8.3 ac & dc logic input levels for differential signals 8.3.1 differential signals definition figure 2. definition of differential ac-swing and "time above ac level" tdvac 8.3.2 differential swing requirement for clock (ck - ck ) and strobe (dqs - dqs ) [ table 9 ] differential ac & dc input levels note : 1. used to define a differential signal slew-rate. 2. for ck - ck use v ih /v il (ac) of add/cmd and v refca ; for dqs - dqs , dqsl - dqsl , dqsu - dqsu use v ih /v il (ac) of dqs and v refdq ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. these values are not defined, however they single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. refe r to "overshoot and undershoot s pecification " [ table 10 ] allowed time before ringback (tdvac) for ck - ck and dqs - dqs symbol parameter ddr3-800/1066/1333/1600 unit note min max v ihdiff differential input high +0.2 note 3 v 1 v ildiff differential input low note 3 -0.2 v 1 v ihdiff (ac) differential input high ac 2 x (v ih (ac)-v ref ) note 3 v 2 v ildiff (ac) differential input low ac note 3 2 x (v ref - v il (ac)) v2 slew rate [v/ns] tdvac [ps] @ |v ih/ldiff (ac)| = 350mv tdvac [ps] @ |v ih/ldiff (ac)| = 300mv min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 - 0.0 tdvac v ih .diff.min half cycle differential input voltage (i.e. dqs-dqs , ck-ck ) time tdvac v ih .diff.ac.min v il .diff.max v il .diff.ac.max - 17 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 8.3.3 single-ended requirements for differential signals each individual component of a different ial signal (ck, dqs, dqsl, dqsu, ck , dqs , dqsl , or dqsu ) has also to comply with certain requirements for single-ended signals. ck and ck have to approximately reach v seh min / v sel max [approximately equal to the ac-levels { v ih (ac) / v il (ac)} for add/cmd signals] in every half-cycle. dqs, dqsl, dqsu, dqs , dqsl have to reach v seh min / v sel max [approximately the ac-levels { v ih (ac) / v il (ac)} for dq signals] in every half-cycle proceeding and following a valid transition. note that the applicable ac-levels for add/cmd and dq?s might be different per speed-bin etc. e.g. if v ih 150(ac)/v il 150(ac) is used for add/cmd sig- nals, then these ac-levels apply also for the single-ended signals ck and ck . figure 3. single-ended requirement for differential signals note that while add/cmd and dq signal requirements are with respect to v ref , the single-ended components of differential signals have a requirement with respect to v dd /2; this is nominally the same. the trans ition of single-ended signals through the ac-lev els is used to measure setup time. for single- ended components of differential signals the requirement to reach v sel max, v seh min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. [ table 11 ] single-ended levels for ck, dqs, dqsl, dqsu, ck , dqs , dqsl , or dqsu note : 1. for ck, ck use v ih /v il (ac) of add/cmd; for strobes (dqs, dqs , dqsl, dqsl , dqsu, dqsu ) use v ih /v il (ac) of dqs. 2. v ih (ac)/v il (ac) for dqs is based on v refdq ; v ih (ac)/v il (ac) for add/cmd is based on v refca ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. these values are not defined, however the single-ended signals ck, ck , dqs, dqs , dqsl, dqsl , dqsu, dqsu need to be within the respective limits (v ih (dc) max, v il (dc)min) for single-ended signals as well as the limitations fo r overshoot and undershoot. refer to "overshoot and undershoot specification" symbol parameter ddr3-800/1066/1333/1600 unit note min max v seh single-ended high-level for strobes (v dd /2)+0.175 note3 v 1, 2 single-ended high-level for ck, ck (v dd /2)+0.175 note3 v 1, 2 v sel single-ended low-level for strobes note3 (v dd /2)-0.175 v1, 2 single-ended low-level for ck, ck note3 (v dd /2)-0.175 v1, 2 v dd or v ddq v seh min v dd /2 or v ddq /2 v sel max v seh v ss or v ssq v sel ck or dqs time - 18 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 8.4 differential input cross point voltage to guarantee tight setup and hold times as well as output skew para meters with respect to clock and strobe, each cross point vo ltage of differential input signals (ck, ck and dqs, dqs ) must meet the requirements in below table. the differential input cross point voltage v ix is measured from the actual cross point of true and complement signal to the mid level between of v dd and v ss . figure 4. vix definition [ table 12 ] cross point voltage for differential input signals (ck, dqs) note : 1. extended range for v ix is only allowed for clock and if single-ended clock input signals ckand ck are monotonic, have a single-ended swing v sel / v seh of at least v dd /2 250 mv, and the differential slew rate of ck-ck is larger than 3 v/ ns. refer to table 11 on page 17 for v sel and v seh standard values. 8.5 slew rate definition for differential input signals see 14.3 ?address/command setup, hold and derating :? on page 48 for single-ended slew rate definitions for address and comman d signals. see 14.4 ?data setup, hold and slew rate derating :? on page 54 for single-ended slew rate definitions for data signals. 8.6 slew rate definitions for differential input signals input slew rate for differential signals (ck, ck and dqs, dqs ) are defined and measured as shown in table 13 and figure 5. [ table 13 ] differential input slew rate definition note : the differential signal (i.e. ck - ck and dqs - dqs ) must be linearbetween these thresholds. figure 5. differential input slew rate definition for dqs, dqs , and ck, ck symbol parameter ddr3-800/1066/1333/1600 unit note min max v ix differential input cross point voltage relative to v dd /2 for ck,ck -150 150 mv -175 175 mv 1 v ix differential input cross point voltage relative to v dd /2 for dqs,dqs -150 150 mv description measured defined by from to differential input slew rate for rising edge (ck-ck and dqs-dqs ) v ildiffmax v ihdiffmin v ihdiffmin - v ildiffmax delta trdiff differential input slew rate for falling edge (ck-ck and dqs-dqs ) v ihdiffmin v ildiffmax v ihdiffmin - v ildiffmax delta tfdiff v dd ck , dqs v dd /2 ck, dqs v ss v ix v ix v ix v ihdiffmin 0 v ildiffmax delta trdiff delta tfdiff - 19 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9. ac & dc output measurement levels 9.1 single-ended ac & dc output levels [ table 14 ] single-ended ac & dc output levels note : 1. the swing of +/-0.1 x v ddq is based on approximately 50% of the static single end ed output high or low swing with a driver impedance of 40 and an effective test load of 25 to v tt =v ddq /2. 9.2 differential ac & dc output levels [ table 15 ] differential ac & dc output levels note : 1. the swing of +/-0.2xv ddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 and an effective test load of 25 to v tt =v ddq /2 at each of the differential outputs. 9.3 single-ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v ol (ac) and v oh (ac) for single ended signals as shown in table 16 and figure 6. [ table 16 ] single-ended output slew rate definition note : output slew rate is verified by design and charac terization, and may not be s ubject to production test. [ table 17 ] single-ended output slew rate description : sr : slew rate q : query output (like in dq, which stands for data-in, query-output) se : single-ended signals for ron = rzq/7 setting figure 6. single-ended output slew rate definition symbol parameter ddr3-800/1066/1333/1600 units note v oh (dc) dc output high measurement level (for iv curve linearity) 0.8 x v ddq v v om (dc) dc output mid measurement level (for iv curve linearity) 0.5 x v ddq v v ol (dc) dc output low measurement level (for iv curve linearity) 0.2 x v ddq v v oh (ac) ac output high measurement level (for output sr) v tt + 0.1 x v ddq v1 v ol (ac) ac output low measurement level (for output sr) v tt - 0.1 x v ddq v1 symbol parameter ddr3-800/1066/1333/1600 units note v ohdiff (ac) ac differential output high measurement level (for output sr) +0.2 x v ddq v1 v oldiff (ac) ac differential output low measurement level (for output sr) -0.2 x v ddq v1 description measured defined by from to single ended output slew rate for rising edge v ol (ac) v oh (ac) v oh (ac)-v ol (ac) delta trse single ended output slew rate for falling edge v oh (ac) v ol (ac) v oh (ac)-v ol (ac) delta tfse parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max single ended output slew rate srqse 2.5 5 2.5 5 2.5 5 tbd 5 v/ns v oh(ac) v ol(ac) delta trse delta tfse v tt - 20 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9.4 differential output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between v oldiff (ac) and v oh- diff (ac) for differential signals as shown in table 18 and figure 7. [ table 18 ] differential output slew rate definition note : output slew rate is verified by design and charac terization, and may not be s ubject to production test. [ table 19 ] differential output slew rate description : sr : slew rate q : query output (like in dq, which stands for data-in, query-output) diff : single-ended signals for ron = rzq/7 setting figure 7. differential output slew rate definition 9.5 reference load for ac timing and output slew rate figure 8 represents the effective reference load of 25 ohms used in defining the relevant ac ti ming parameters of the device as well as output slew rate measurements. it is not intended as a precise representati on of any particular system environment or a depiction of the actual load presented by a production tester. sys- tem designers should use ibis or other simu lation tools to correlate the timing refe rence load to a system environment. manufac turers correlate to their production test conditions, generally one or more coaxial tr ansmission lines terminated at the tester electronics. figure 8. reference load for ac timing and output slew rate description measured defined by from to differential output slew rate for rising edge v oldiff (ac) v ohdiff (ac) v ohdiff (ac)-v oldiff (ac) delta trdiff differential output slew rate for falling edge v ohdiff (ac) v oldiff (ac) v ohdiff (ac)-v oldiff (ac) delta tfdiff parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units min max min max min max min max differential output slew rate srqse 5 10 5 10 5 10 tbd 10 v/ns v ohdiff (ac) v oldiff (ac) delta trdiff delta tfdiff v tt v ddq dut dq dqs dqs v tt = v ddq /2 25 ck/ck reference point - 21 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9.6 overshoot/undershoot specification 9.6.1 address and control overshoot and undershoot specifications [ table 20 ] ac overshoot/undershoot specification for address and control pins (a0-a12, ba0-ba2. cs . ras . cas . we . cke, odt) figure 9. address and control overshoot and undershoot definition 9.6.2 clock, data, strobe and mask overshoot and undershoot specifications [ table 21 ] ac overshoot/undershoot specification for clock, data, strobe and mask (dq, dqs, dqs , dm, ck, ck ) figure 10. clock, data, strobe and mask overshoot and undershoot definition parameter specification unit ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure 9) 0.4v 0.4v 0.4v 0.4v v maximum peak amplitude allowed for undershoot area (see figure 9) 0.4v 0.4v 0.4v 0.4v v maximum overshoot area above v dd (see figure 9) 0.67v-ns 0.5v-ns 0.4v-ns 0.33v-ns v-ns maximum undershoot area below v ss (see figure 9) 0.67v-ns 0.5v-ns 0.4v-ns 0.33v-ns v-ns parameter specification unit ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 maximum peak amplitude allowed for overshoot area (see figure 10) 0.4v 0.4v 0.4v 0.4v v maximum peak amplitude allowed for undershoot area (see figure 10) 0.4v 0.4v 0.4v 0.4v v maximum overshoot area above v ddq (see figure 10) 0.25v-ns 0.19v-ns 0.15v-ns 0.13v-ns v-ns maximum undershoot area below v ssq (see figure 10) 0.25v-ns 0.19v-ns 0.15v-ns 0.13v-ns v-ns overshoot area maximum amplitude v dd undershoot area maximum amplitude v ss volts (v) time (ns) overshoot area maximum amplitude v ddq undershoot area maximum amplitude v ssq volts (v) time (ns) - 22 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9.7 34ohm output driver dc electrical characteristics a functional representation of the output buffer is shown below. output driver impedanc e ron is defined by the value of externa l reference resistor rzq as follows: ron 34 = rzq/7 (nominal 34.3ohms +/- 10% with nominal rzq=240ohm) the individual pull-up and pull-down resistor s (ronpu and ronpd) are defined as follows figure 11. output driver : definition of voltages and currents [ table 22 ] output driver dc electrical characteristics, assuming rzq=240ohms ; entire operating temperature range ; after proper zq calibration note : 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity 2. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss 3. pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 x v ddq . other calibration schemes may be us ed to achieve the linearity spec shown above, e.g. calibration at 0.2 x v ddq and 0.8 x v ddq 4. measurement definition for mismatch between pull-up and pu ll-down, mmpupd: measure ronpu and ronpd. both at 0.5 x v ddq : ronnom resistor vout min nom max units note 34ohms ron34pd v oldc = 0.2 x v ddq 0.6 1.0 1.1 rzq/7 1,2,3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 1,2,3 v ohdc = 0.8 x v ddq 0.9 1.0 1.4 1,2,3 ron34pu v oldc = 0.2 x v ddq 0.9 1.0 1.4 1,2,3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 1,2,3 v ohdc = 0.8 x v ddq 0.6 1.0 1.1 1,2,3 40ohms ron40pd v oldc = 0.2 x v ddq 0.6 1.0 1.1 rzq/6 1,2,3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 1,2,3 v ohdc = 0.8 x v ddq 0.9 1.0 1.4 1,2,3 ron40pu v oldc = 0.2 x v ddq 0.9 1.0 1.4 1,2,3 v omdc = 0.5 x v ddq 0.9 1.0 1.1 1,2,3 v ohdc = 0.8 x v ddq 0.6 1.0 1.1 1,2,3 mismatch between pull-up and pull-down, mmpupd v omdc = 0.5 x v ddq -10 10 % 1,2,4 ronpu = v ddq -v out l iout l under the condition that ronpd is turned off ronpd = v out l iout l under the condition that ronpu is turned off v ddq dq v ssq ron pu ipd ron pd to other circuity output driver ipu iout vout mmpupd = ronpu - ronpd x 100 ronnom - 23 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9.7.1 output drive temperature and voltage sensitivity if temperature and/or voltage change after calibration, the tolerance limits widen according to table 23 and table 24. t = t - t(@calibration); v = v ddq - v ddq (@calibration); v dd = v ddq *dr on dt and dr on dv are not subject to production test but are verified by design and characterization [ table 23 ] output driver sensitivity definition [ table 24 ] output driver voltage and temperature sensitivity 9.8 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is defined by bits a9, a6 and a2 of mr1 register. odt is applied to the dq,dm, dqs/dqs and tdqs,tdqs (x8 devices only) pins. a functional representation of the on-die termination is show n below. the individual pull-up and pull-down resistors (rttpu and rttpd) are defined as follows : chip in termination mode figure 12. on-die termination : definition of voltages and currents min max units ronpu@v ohdc 0.6 - dr on dth * | t| - dr on dvh * | v| 1.1 + dr on dth * | t| + dr on dvh * | v| rzq/7 ron@v omdc 0.9 - dr on dtm * | t| - dr on dvm * | v| 1.1 + dr on dtm * | t| + dr on dvm * | v| rzq/7 ronpd@ voldc 0.6 - dr on dtl * | t| - dr on dvl * | v| 1.1 + dr on dtl * | t| + dr on dvl * | v| rzq/7 speed bin 800/1066/1333 1600 units min max min max dr on dtm 01.501.5 %/ c dr on dvm 0 0.15 0 0.13 %/mv dr on dtl 01.501.5 %/ c dr on dvl 0 0.15 0 0.13 %/mv dr on dth 01.501.5 %/ c dr on dvh 0 0.15 0 0.13 %/mv rttpu = v ddq -v out l iout l under the condition that rttpd is turned off rttpd = v out l iout l under the condition that rttpu is turned off v ddq dq v ssq rtt pu ipd rtt pd to other circuitry like rcv, ... odt ipu iout v out iout=ipd-ipu - 24 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9.8.1 odt dc electrical characteristics table 25 provides and overview of the odt dc elec trical characteristics. they values for rtt 60pd120, rtt 60pu120, rtt 120pd240, rtt 120pu240, rtt 40pd80, rtt 40pu80, rtt 30pd60, rtt 30pu60, rtt 20pd40, rtt 20pu40 are not specification requirements, but can be used as design guide lines: [ table 25 ] odt dc electrical characteristics, assuming rzq=240ohm +/- 1% entire operating temperature range; after proper zq calibration mr1 (a9,a6,a2) rtt resistor vout min nom max unit note (0,1,0) 120 ohm rtt 120pd240 v ol (dc) 0.2xv ddq 0.6 1.0 1.1 r zq 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq 1,2,3,4 v oh (dc) 0.8xv ddq 0.9 1.0 1.4 r zq 1,2,3,4 rtt 120pu240 v ol (dc) 0.2xv ddq 0.9 1.0 1.4 r zq 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq 1,2,3,4 v oh (dc) 0.8xv ddq 0.6 1.0 1.1 r zq 1,2,3,4 rtt 120 v il (ac) to v ih (ac) 0.9 1.0 1.6 r zq /2 1,2,5 (0,0,1) 60 ohm rtt 60pd240 v ol (dc) 0.2xv ddq 0.6 1.0 1.1 r zq /2 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /2 1,2,3,4 v oh (dc) 0.8xv ddq 0.9 1.0 1.4 r zq /2 1,2,3,4 rtt 60pu240 v ol (dc) 0.2xv ddq 0.9 1.0 1.4 r zq /2 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /2 1,2,3,4 v oh (dc) 0.8xv ddq 0.6 1.0 1.1 r zq /2 1,2,3,4 rtt 60 v il (ac) to v ih (ac) 0.9 1.0 1.6 r zq /4 1,2,5 (0,1,1) 40 ohm rtt 40pd240 v ol (dc) 0.2xv ddq 0.6 1.0 1.1 r zq /3 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /3 1,2,3,4 v oh (dc) 0.8xv ddq 0.9 1.0 1.4 r zq /3 1,2,3,4 rtt 40pu240 v ol (dc) 0.2xv ddq 0.9 1.0 1.4 r zq /3 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /3 1,2,3,4 v oh (dc) 0.8xv ddq 0.6 1.0 1.1 r zq /3 1,2,3,4 rtt 40 v il (ac) to v ih (ac) 0.9 1.0 1.6 r zq /6 1,2,5 (1,0,1) 30 ohm rtt 60pd240 v ol (dc) 0.2xv ddq 0.6 1.0 1.1 r zq /4 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /4 1,2,3,4 v oh (dc) 0.8xv ddq 0.9 1.0 1.4 r zq /4 1,2,3,4 rtt60 pu240 v ol (dc) 0.2xv ddq 0.9 1.0 1.4 r zq /4 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /4 1,2,3,4 v oh (dc) 0.8xv ddq 0.6 1.0 1.1 r zq /4 1,2,3,4 rtt 60 v il (ac) to v ih (ac) 0.9 1.0 1.6 r zq /8 1,2,5 (1,0,0) 20 ohm rtt 60pd240 v ol (dc) 0.2xv ddq 0.6 1.0 1.1 r zq /6 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /6 1,2,3,4 v oh (dc) 0.8xv ddq 0.9 1.0 1.4 r zq /6 1,2,3,4 rtt 60pu240 v ol (dc) 0.2xv ddq 0.9 1.0 1.4 r zq /6 1,2,3,4 0.5xv ddq 0.9 1.0 1.1 r zq /6 1,2,3,4 v oh (dc) 0.8xv ddq 0.6 1.0 1.1 r zq /6 1,2,3,4 rtt 60 v il (ac) to v ih (ac) 0.9 1.0 1.6 r zq /12 1,2,5 deviation of v m w.r.t v ddq /2, vm -5 5 % 1,2,5,6 - 25 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e note : 1. the tolerance limits are specified after calibration with stable voltage and temperature. for the behavior of the tolerance limits if temperature or voltage changes after calibra- tion, see following section on voltage and temperature sensitivity 2. the tolerance limits are specified under the condition that v ddq = v dd and that v ssq = v ss 3. pull-down and pull-up odt resistors are recommended to be calibrated at 0.5xv ddq . other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2xv ddq and 0.8xv ddq . 4. not a specification requirement, but a design guide line 5. measurement definition for rtt: apply v ih (ac) to pin under test and measure current i(v ih (ac)), then apply v il (ac) to pin under test and measure current i(v il (ac)) respectively 6. measurement definition for v m and v m : measure voltage (v m ) at test pin (midpoint) with no load 9.8.2 odt temperature and voltage sensitivity if temperature and/or voltage change after calibration, th e tolerance limits widen according to table below t = t - t(@calibration); v = v ddq - v ddq (@calibration); v dd = v ddq [ table 26 ] odt sensitivity definition [ table 27 ] odt voltage and temperature sensitivity note : these parameters may not be subject to production te st. they are verified by design and characterization. min max units rtt 0.9 - dr tt dt * | t| - dr tt dv * | v| 1.6 + dr tt dt * | t| + dr tt dv * | v| rzq/2,4,6,8,12 min max units dr tt dt 01.5 %/ c dr tt dv 00.15%/mv rtt = v ih (ac) - v il (ac) i(v ih (ac)) - i(v il (ac)) v m = 2 x v m v ddq x 100 - 1 - 26 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 9.9 odt timing definitions 9.9.1 test load for odt timings different than for timing measurements, the refe rence load for odt timings is defined in figure 13. figure 13. odt timing reference load 9.9.2 odt timing definitions definitions for taon, taonpd, taof, taofpd and tadc are provided in table 28 and subs equent figures. measurement reference sett ings are provided in table 29 . [ table 28 ] odt timing definitions [ table 29 ] reference settings for odt timing measurements symbol begin point definition end point definition figure taon rising edge of ck - ck defined by the end point of odtlon extrapolated point at v ssq figure 14 taonpd rising edge of ck - ck with odt being first registered high extrapolated point at v ssq figure 15 taof rising edge of ck - ck defined by the end point of odtloff end point: extrapolated point at v rtt_nom figure 16 taofpd rising edge of ck - ck with odt being first registered low end point: extrapolated point at v rtt_nom figure 17 tadc rising edge of ck - ck defined by the end point of odtlcnw, odtlcwn4 of odtlcwn8 end point: extrapolated point at v rtt_wr and v rtt_nom respectively figure 18 measured parameter rtt_nom setting rtt_wr setting v sw1 [v] v sw2 [v] note taon r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 taonpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 taof r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 taofpd r zq /4 na 0.05 0.10 r zq /12 na 0.10 0.20 tadc r zq /12 r zq /2 0.20 0.30 v ddq ck,ck dut dq, dm dqs , dqs tdqs , tdqs rtt =25 ohm v tt = v ssq timing reference points v ssq - 27 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 14. definition fo taon figure 15. difinition of taonpd figure 16. definition of taof ck ck begin point : rising edge of ck - ck defined by the end point of odtlon t aon v tt dq, dm dqs , dqs tdqs , tdqs v ssq t sw1 t sw2 v sw1 v sw2 end point extrapolated point at v ssq v ssq ck ck begin point : rising edge of ck - ck with odt being first registered high t aonpd v tt dq, dm dqs , dqs tdqs , tdqs v ssq t sw1 t sw2 v sw1 v sw2 end point extrapolated point at v ssq v ssq ck ck begin point : rising edge of ck - ck defined by the end point of odtloff t aof v tt dq, dm dqs , dqs tdqs , tdqs v rtt_nom t sw1 t sw2 v sw1 v sw2 end point extrapolated point at v rtt_nom v ssq td_taon_def - 28 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 17. definition of taofpd figure 18. definition of tadc ck ck begin point : rising edge of ck - ck with odt being first registered low t aofpd v tt dq, dm dqs , dqs tdqs , tdqs v rtt_nom t sw1 t sw2 v sw1 v sw2 end point extrapolated point at v rtt_nom v ssq ck ck begin point : rising edge of ck - ck defined by the end point of odtlcnw t adc v tt dq, dm dqs , dqs tdqs , tdqs v rtt_nom t sw11 t sw21 v sw1 end point extrapolated point at v rtt_nom v rtt_wr end point extrapolated point at v rtt_wr t adc v sw2 begin point : rising edge of ck - ck defined by the end point of odtlcwn4 or odtlcwn8 end point extrapolated point at v rtt_nom t sw12 t sw22 v rtt_nom v ssq - 29 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 10. idd current measure method 10.1 idd measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patterns are defined. figure 19 shows the setup and test load for idd and iddq measurements. - idd currents (such as idd0, idd1, idd2n, idd2nt, idd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and idd7) are measured as time-averaged currents with all v dd balls of the ddr3 sdram under test tied toget her. any iddq current is not included in idd currents. - iddq currents (such as iddq2nt and iddq4r) are measured as time-averaged currents with all v ddq balls of the ddr3 sdram under test tied together. any idd current is not included in iddq currents. attention : iddq values cannot be directly used to calc ulate io power of the ddr3 sdram. they can be used to support correlation of simulat ed io power to actual io power as outlined in figure 20. in dram module application, iddq cannot be measured separately since v dd and v ddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply : - "0" and "low" is defined as v in <= v il ac(max). - "1" and "high" is defined as v in >= v ih ac(min). - "floating" is defined as inputs are v ref = v dd / 2. - ?$paratext> are provided in table 30 - ?$paratext> are described in table 31 - detailed idd and iddq measurement-loop patterns are described in table 32 on page 31 through table 39. - idd measurements are done after properly initializing the ddr3 sdram. this includes but is not limited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 - attention : the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measurement is star ted. - define d = {cs , ras , cas , we } := {high, low, low, low} - define d = {cs , ras , cas , we } := {high, high, high, high} - reset stable time is : during a cold bood reset (initializati on), current reading is valid once power is stable and reset has been low for 1ms; during warm boot reset(while operating), current reading is valid after reset has been low for 200ns + trfc [ table 30 ] timing used for idd and iddq measured - loop patterns parameter bin ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 unit 5-5-5 6-6-6 6-6-6 7-7-7 8-8-8 7-7-7 8-8-8 9-9-9 10-10-10 8-8-8 9-9-9 10-10-10 11-11-11 tckmin(idd) 2.5 1.875 1.5 1.25 ns cl(idd) 5 6 6 7 8 7 8 9 10 8 9 10 11 nck trcdmin(idd) 56678789 10 89 10 11nck trcmin(idd) 20 21 26 27 28 31 32 33 34 36 37 38 39 nck trasmin(idd) 15 20 24 28 nck trpmin(idd) 5 6 6 7 8 7 8 9 10 8 9 10 11 nck tfaw(idd) x4/x8 16 20 20 24 nck x16 20 27 30 32 nck trrd(idd) x4/x8 4 4 4 5 nck x16 4 6 5 6 nck trfc(idd) - 512mb 36 48 60 72 nck trfc(idd) - 1gb 44 59 74 88 nck trfc(idd) - 2gb 64 86 107 128 nck trfc(idd) - 4gb 120 160 200 240 nck trfc(idd) - 8gb 140 187 234 280 nck - 30 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 19. measurement setup and test load for idd and iddq measurements figure 20. correlation from simulated channel io power to actual channel io power supported by iddq measurement. i ddq i dd v dd v ddq reset ck/ck cke cs ras , cas , we a, ba odt zq v ss v ssq dqs, dqs dq, dm, tdqs, tdqs v ddq /2 r tt = 25 ohm [ note : dimm level output test load condition may be different from above] application specific memory channel environment channel io power simulation iddq measurement correlation correction channel io power number iddq test load iddq simulation - 31 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 31 ] basic idd and iddq measurement conditions symbol description idd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 30 on page 29 ; bl : 8 1) ; al : 0; cs : high between act and pre; command, address, bank address inputs: partially toggling according to table 32 on page 31 ; data io: floating; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 32); output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 32 idd1 operating one bank active-read-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 30 on page 29 ; bl : 8 1) ; al : 0; cs : high between act, rd and pre; command, address, bank address inputs, data io: partially toggling according to table 33 on page 32 ; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 33); output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 33 idd2n precharge standby current cke: high; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially tog- gling according to table 34 on page 32 ; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 34 idd2nt precharge standby odt current cke: high; external clock: on; tck, cl : see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially tog- gling according to table 35 on page 33 ; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: toggling according to table 35 ; pattern details: see table 35 iddq2nt precharge standby odt iddq current same definition like for idd2nt, however measuring iddq current instead of idd current idd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pre- charge power down mode: slow exi 3) idd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 30 on page 29; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pre- charge power down mode: fast exit 3) idd2q precharge quiet standby current cke: high; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0 idd3n active standby current cke: high; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially tog- gling according to table 34 on page 32 ; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 34 idd3p active power-down current cke: low; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm :stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0 idd4r operating burst read current cke: high; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : high between rd; command, address, bank address inputs: par- tially toggling according to table 36 on page 33 ; data io: seamless read data burst with different data between one burst and the next one according to table 36 ; dm: stable at 0; bank activity: all banks open, rd commands cycling through banks: 0,0,1,1,2,2,... (see table 7 on page 14); output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 36 iddq4r operating burst read iddq current same definition like for idd4r, however measuring iddq current instead of idd current idd4w operating burst write current cke: high; external clock: on; tck, cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : high between wr; command, address, bank address inputs: par- tially toggling according to table 37 on page 34 ; data io: seamless write data burst with different data between one burst and the next one according to table 37; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,... (see table 37); output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at high ; pattern details: see table 37 idd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs : high between ref; command, address, bank address inputs: partially toggling according to table 38 on page 34 ; data io: floating; dm: stable at 0; bank activity: ref command every nrfc (see table 38); output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 38 idd6 self refresh current: normal temperature range tcase: 0 - 85c; auto self-refresh (asr): disabled 4) ; self-refresh temperature range (srt): n ormal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: self- refresh operation; output buffer and rtt: enabled in mode registers 2) ; odt signal: floating - 32 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 31 ] basic idd and iddq measurement conditions note : 1) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b 2) output buffer enable: set mr1 a[12] = 0b; set mr1 a[5,1] = 01 b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b 3) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12=1b for fast exit 4) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature 5) self-refresh temperature range (srt): set mr2 a7=0b for normal or 1b for extended temperature range 6) refer to dram supplier data sheet and/or dimm spd to determine if optional features or requirements are supported by ddr3 sd ram device 7) read burst type : nibble sequential, set mr0 a[3]=0b symbol description idd6et self-refresh current: extended temperature range (optional) 6) tcase: 0 - 95c; auto self-refresh (asr): disabled 4) ; self-refresh temperature range (srt): extended 5) ; cke: low; external clock: off; ck and ck : low; cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: extended temperature self-refresh operation; output buffer and rtt: enabled in mode registers 2) ; odt signal: floating idd6tc auto self-refresh current (optional) 6) tcase: 0 - 95c; auto self-refresh (asr): enabled 4) ; self-refresh temperature range (srt): normal 5) ; cke: low; external clock: off; ck and ck : low; cl: see table 30 on page 29 ; bl: 8 1) ; al: 0; cs , command, address, bank address, data io: floating; dm: stable at 0; bank activity: auto self-refresh operation; output buffer and rtt: enabled in mode registers 2) ; odt signal: floating idd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 30 on page 29 ; bl: 8 1) ; al: cl-1; cs : high between act and rda; command, address, bank address inputs: partially toggling according to table 39 on page 35 ; data io: read data bursts with different data between one burst and the next one according to table 39 ; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see table 39 ; output buffer and rtt: enabled in mode registers 2) ; odt signal: stable at 0; pattern details: see table 39 idd8 reset low current reset : low; external clock : off; ck and ck : low; cke : floating ; cs , command, address, bank address, data io : floating ; odt signal : floating - 33 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 32 ] idd0 measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are mid-level. 2. dq signals are mid-level. ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 act00110 0 000000 - 1,2 d, d10000 0 000000 - 3,4 d , d 11110 0 000000 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre00100 0 000000 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc + 0 act00110 0 00 0 0 f 0- 1*nrc + 1, 2 d, d10000 0 00 0 0 f 0- 1*nrc + 3, 4 d , d 11110 0 00 0 0 f 0- ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc + nraspre00100 0 00 0 0 f 0 ... repeat 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead - 34 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 33 ] idd1 measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. 2. burst sequence driven on each dq signal by read command . outside burst operation, dq signals are mid-level. [ table 34 ] idd2 and idd3n measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are mid-level. 2. dq signals are mid-level. ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 act 00110 0 000000 - 1,2 d, d 10000 0 000000 - 3,4 d , d 11110 0 000000 - ... repeat pattern 1...4 until nrcd- 1, truncate if necessary nrcd rd 01010 0 000000 00000000 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 00100 0 000000 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 00110 0 00 0 0 f 0- 1*nrc + 1, 2 d, d 10000 0 00 0 0 f 0- 1*nrc + 3, 4 d , d 11110 0 00 0 0 f 0- ... repeat pattern nrc + 1,..., 4 until nrc + nrcd - 1, truncate if necessary 1*nrc + nrcd rd 01010 0 00 0 0 f 0 00110011 ... repeat pattern nrc + 1,..., 4 until nrc +nras - 1, truncate if necessary 1*nrc + nras pre 00100 0 00 0 0 f 0- ... repeat pattern nrc + 1,..., 4 until 2 * nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 d 10000 0 000000 - 1 d 10000 0 000000 - 2d 11110 0 00 0 0 f 0- 3d 11110 0 00 0 0 f 0- 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-27 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead - 35 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 35 ] idd2nt and iddq2nt measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are mid-level. 2. dq signals are mid-level. [ table 36 ] idd4r and iddq4r measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. 2. burst sequence driven on each dq signal by write comm and. outside burst operation, dq signals are mid-level. ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 d 10000 0 000000 - 1 d 10000 0 000000 2d 11110 0 00 0 0 f 0 3d 11110 0 00 0 0 f 0 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-27 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7 ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 rd 01010 0 000000 00000000 1 d 10000 0 000000 - 2,3 d ,d 11110 0 000000 - 4 rd 01010 0 00 0 0 f 0 00110011 5 d 10000 0 00 0 0 f 0- 6,7 d ,d 11110 0 00 0 0 f 0- 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 - 36 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 37 ] idd4w measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise mid-level. 2. burst sequence driven on each dq signal by write comm and. outside burst operation, dq signals are mid-level. [ table 38 ] idd5b measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are mid-level. 2. dq signals are mid-level. ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 wr 01001 0 000000 00000000 1 d 10001 0 000000 - 2,3 d ,d 11111 0 000000 - 4 wr 01001 0 00 0 0 f 0 00110011 5 d 10001 0 00 0 0 f 0- 6,7 d ,d 11111 0 00 0 0 f 0- 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7 ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 ref 00010 0 000000 - 1 1,2 d 10000 0 000000 - 3,4 d ,d 11110 0 00 0 0 f 0 - 5...8 repeat cycles 1...4, but ba[2:0] = 1 9...12 repeat cycles 1...4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc - 1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary. - 37 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 39 ] idd7 measurement - loop pattern 1) note : 1. dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise mid-level. 2. burst sequence driven on each dq signal by read command . outside burst operation. dq signals are mid-level. ck/ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data 2) toggling static high 0 0 act 00110 0 00 0 0 0 0- 1 rda 01010 0 00 1 0 0 0 00000000 2 d 10000 0 00 0 0 0 0- ... repeat above d command until nrrd - 1 1 nrrd act 00110 1 00 0 0 f 0- nrrd + 1 rda 01010 1 00 1 0 f 0 00110011 nrrd + 2 d 10000 1 00 0 0 f 0- ... repeat above d command until 2*nrrd-1 2 2 * nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3 * nrrd repeat sub-loop 1, but ba[2:0] = 3 44 * nrrd d 10000 3 00 0 0 f 0- assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd d 10000 7 00 0 0 f 0- assert and repeat above d command until 2*nfaw - 1, if necessary 10 2*nfaw+0 act 00110 0 00 0 0 f 0- 2*nfaw+1 rda 01010 0 00 1 0 f 0 00110011 2*nfaw+2 d 10000 0 00 0 0 f 0- repeat above d command until 2*nfaw + nrrd - 1 11 2*nfaw+nrrd act 00110 1 00 0 0 0 0- 2*nfaw+nrrd+1 rda 01010 1 00 1 0 0 0 00000000 2*nfaw+nrrd+2 d 10000 1 00 0 0 0 0- repeat above d command until 2*nfaw + 2*nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d 10000 3 00 0 0 0 0- assert and repeat above d command until 3*nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 19 3*nfaw+4*nrrd d 10000 7 00 0 0 0 0- assert and repeat above d command until 4*nfaw - 1, if necessary - 38 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 11.0 1gb ddr3 sdram e-die idd specification table [ table 40 ] idd specification for 1gb ddr3 e-die symbol 256mx4 (k4b1g0446e) unit note ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 6-6-6 7-7-7 9-9-9 11-11-11 idd0 55 60 65 70 ma idd1 70 75 80 85 ma idd2p0(slow exit) 10 10 10 10 ma idd2p1(fast exit)25252525ma idd2n30303540ma idd2nt 30 35 40 45 ma iddq2nt45454545ma idd2q25303540ma idd3p(fast exit) 25 25 25 30 ma idd3n40455055ma idd4r 85 100 115 130 ma iddq4r 35 35 35 35 ma idd4w 85 105 125 140 ma idd5b 150 150 160 170 ma idd6 10 10 10 10 ma idd7 170 180 225 250 ma idd8 10 10 10 10 ma symbol 128mx8 (k4b1g0846e) unit note ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 6-6-6 7-7-7 9-9-9 11-11-11 idd0 55 60 65 70 ma idd1 70 75 80 85 ma idd2p0(slow exit) 10 10 10 10 ma idd2p1(fast exit)25252525ma idd2n30303540ma idd2nt 30 35 40 45 ma iddq2nt70707070ma idd2q25303540ma idd3p(fast exit) 25 25 25 30 ma idd3n40455055ma idd4r 95 110 125 140 ma iddq4r 50 50 50 50 ma idd4w 85 115 135 150 ma idd5b 150 150 160 170 ma idd6 10 10 10 10 ma idd7 170 185 230 260 ma idd8 10 10 10 10 ma - 39 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e symbol 64mx16 (K4B1G1646E) unit note ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 6-6-6 7-7-7 9-9-9 11-11-11 idd0 tbd 65 70 75 ma idd1 tbd 85 90 95 ma idd2p0(slow exit) tbd 10 10 10 ma idd2p1(fast exit) tbd 25 25 25 ma idd2n tbd 30 35 40 ma idd2nt tbd 35 40 45 ma iddq2nt tbd 145 145 145 ma idd2q tbd 30 35 40 ma idd3p(fast exit) tbd 25 27 40 ma idd3n tbd 45 50 55 ma idd4r tbd 130 160 180 ma iddq4r tbd 105 105 105 ma idd4w tbd 130 155 190 ma idd5b tbd 150 160 170 ma idd6 tbd 10 10 10 ma idd7 tbd 200 240 270 ma idd8 tbd 10 10 10 ma - 40 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 12. input/output capacitance [ table 41 ] input/output capacitance note : 1. although the dm, tdqs and tdqs pins have different functions, the loading matches dq and dqs 2. this parameter is not subject to production test. it is verified by design and characterization. the capacitance is measured according to jep147("procedure for me asuring input capacitance using a vector network analyzer( vna )") with v dd , v ddq , v ss , v ssq applied and all other pins floating (except the pin under test, cke, reset and odt as necessary). v dd =v ddq =1.5v, v bias =v dd /2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of cck- cck 5. absolute value of cio(dqs)-cio( dqs ) 6. ci applies to odt, cs , cke, a0-a15, ba0-ba2, ras , cas , we . 7. cdi_ctrl applies to odt, cs and cke 8. cdi_ctrl=ci(ctrl)-0.5*(ci(clk)+ci( clk )) 9. cdi_add_cmd applies to a0-a15, ba0-ba2, ras , cas and we 10. cdi_add_cmd=ci(add_cmd) - 0.5*(ci(clk)+ci( clk )) 11. cdio=cio(dq,dm) - 0.5*(cio(dqs)+cio( dqs )) 12. maximum external load capacitance on zq pin: 5pf parameter symbol ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units note min max min max min max min max input/output capacitance (dq, dm, dqs, dqs , tdqs, tdqs ) cio 1.5 3.0 1.5 2.7 1.5 2.5 1.5 2.3 pf 1,2,3 input capacitance (ck and ck) cck 0.8 1.6 0.8 1.6 0.8 1.4 0.8 1.4 pf 2,3 input capacitance delta (ck and ck) cdck 0 0.15 0 0.15 0 0.15 0 0.15 pf 2,3,4 input capacitance (all other input-only pins) ci 0.75 1.5 0.75 1.5 0.75 1.3 0.75 1.3 pf 2,3,6 input capacitance delta (dqs and dqs) cddqs 0 0.2 0 0.2 0 0.15 0 0.15 pf 2,3,5 input capacitance delta (all control input-only pins) cdi_ctrl -0.5 0.3 -0.5 0.3 -0.4 0.2 -0.4 0.2 pf 2,3,7,8 input capacitance delta (all add and cmd input-only pins) cdi_add_cmd -0.5 0.5 -0.5 0.5 -0.4 0.4 -0.4 0.4 pf 2,3,9,10 input/output capacitance delta (dq, dm, dqs, dqs , tdqs, tdqs ) cdio -0.5 0.3 -0.5 0.3 -0.5 0.3 -0.5 0.3 pf 2,3,11 input/output capacitance of zq pin czq - 3 - 3 - 3 - 3 pf 2, 3, 12 - 41 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 13. electrical characteristics and ac timing for ddr3-800 to ddr3-1600 13.1 clock specification the jitter specified is a random jitter meeti ng a gaussian distribution. input clocks vi olating the min/max values may result i n malfunction of the ddr3 sdram device. 13.1.1 definition for tck(avg) tck(avg) is calculated as the average clo ck period across any consecutive 200 cycle wi ndow, where each clock period is calculat ed from rising edge to rising edge. 13.1.2 definition for tck(abs) tck(abs) is defind as the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tck(abs) is not subject to produc- tion test. 13.1.3 definition for tch(avg) and tcl(avg) tch(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tcl(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: 13.1.4 definition for note for tjit(per), tjit(per, ick) tjit(per) is defined as the largest deviation of any single tck from tck(avg). tjit(per ) = min/max of {tcki-tck(avg) where i=1 to 200} tjit(per) defines the single period ji tter when the dll is already locked. tjit(per,lck) uses the same definition for singl e period jitter, during the dll locking period only. tjit(per) and tjit(per,lck) are not subject to production test. 13.1.5 definition for tjit(cc), tjit(cc, ick) tjit(cc) is defined as th e absolute difference in clock period between two cons ecutive clock cycles: tj it(cc) = max of {tcki+1 -tcki} tjit(cc) defines the cycl e to cycle jitter when the dll is already locked. tjit(cc,lck) uses the same def inition for cycle to cycle jitter, during the dll locking period only. tjit(cc) and tjit(cc,lck) are not subject to production test. 13.1.6 definition for terr(nper) terr is defined as the cumulative error across n multiple consecut ive cycles from tck(avg). terr is not subject to production t est. n j=1 tckj n n=200 - 42 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 13.2 refresh parameters by device density [ table 42 ] refresh parameters by device density note : 1. users should refer to the dram supplier data sheet and/or t he dimm spd to determine if ddr3 sdram devices support the follow ing options or requirements referred to in this material. 13.3 speed bins and cl, trcd, trp, trc and tras for corresponding bin ddr3 sdram speed bins include tck, trcd, trp, tras and trc for each corresponding bin. [ table 43 ] ddr3-800 speed bins [ table 44 ] ddr3-1066 speed bins parameter symbol 1gb 2gb 4gb 8gb units note all bank refresh to active/refresh cmd time trfc 110 160 300 350 ns average periodic refresh interval trefi 0 c t case 85 c 7.8 7.8 7.8 7.8 s 85 c < t case 95 c 3.9 3.9 3.9 3.9 s 1 speed ddr3-800 units note cl-nrcd-nrp 6 - 6 - 6 parameter symbol min max internal read command to first data taa 15 20 ns act to internal read or write delay time trcd 15 - ns pre command period trp 15 - ns act to act or ref command period trc 52.5 - ns act to pre command period tras 37.5 9*trefi ns 8 cl = 6 / cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3 supported cl settings 6 nck supported cwl settings 5 nck speed ddr3-1066 units note cl-nrcd-nrp 7 - 7 - 7 parameter symbol min max internal read command to first data taa 13.125 20 ns act to internal read or write delay time trcd 13.125 - ns pre command period trp 13.125 - ns act to act or ref command period trc 50.625 - ns act to pre command period tras 37.5 9*trefi ns cl = 6 cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3,6 cwl = 6 tck(avg) reserved ns 1,2,3,4 cl = 7 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,4 cl = 8 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3 supported cl settings 6,7,8 nck supported cwl settings 5,6 nck - 43 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 45 ] ddr3-1333 speed bins speed ddr3-1333 units note cl-nrcd-nrp 9 -9 - 9 parameter symbol min max internal read command to first data taa 13.5 (13.125) 5,9 20 ns act to internal read or write delay time trcd 13.5 (13.125) 5,9 - ns pre command period trp 13.5 (13.125) 5,9 - ns act to act or ref command period trc 49.5 (49.125) 5,9 - ns act to pre command period tras 36 9*trefi ns cl = 6 cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 tck(avg) reserved ns 1,2,3,4,7 cwl = 7 tck(avg) reserved ns 4 cl = 7 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,4,7 (optional) note 5,9 cwl = 7 tck(avg) reserved ns 1,2,3,4, cl = 8 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,7 cwl = 7 tck(avg) reserved ns 1,2,3,4, cl = 9 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 6,7,8,9 nck supported cwl settings 5,6,7 nck - 44 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 46 ] ddr3-1600 speed bins speed ddr3-1600 units note cl-nrcd-nrp 11-11-11 parameter symbol min max internal read command to first data taa 13.75 (13.125) 5,9 20 ns act to internal read or write delay time trcd 13.75 (13.125) 5,9 - ns pre command period trp 13.75 (13.125) 5,9 - ns act to act or ref command period trc 48.75 (48.125) 5,9 - ns act to pre command period tras 35 9*trefi ns cl = 6 cwl = 5 tck(avg) 2.5 3.3 ns 1,2,3,8 cwl = 6 tck(avg) reserved ns 1,2,3,4,8 cwl = 7, 8 tck(avg) reserved ns 4 cl = 7 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,4,8 (optional) note 5,9 cwl = 7 tck(avg) reserved ns 1,2,3,4,8 cwl = 8 tck(avg) reserved ns 4 cl = 8 cwl = 5 tck(avg) reserved ns 4 cwl = 6 tck(avg) 1.875 <2.5 ns 1,2,3,8 cwl = 7 tck(avg) reserved ns 1,2,3,4,8 cwl = 8 tck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,4,8 (optional) note 9 cwl = 8 tck(avg) reserved ns 1,2,3,4 cl = 10 cwl = 5,6 tck(avg) reserved ns 4 cwl = 7 tck(avg) 1.5 <1.875 ns 1,2,3,8 cwl = 8 tck(avg) reserved ns 1,2,3,4 cl = 11 cwl = 5,6,7 tck(avg) reserved ns 4 cwl = 8 tck(avg) 1.25 <1.5 ns 1,2,3,5 supported cl settings 6,7,8,9,11 nck supported cwl settings 5,6,7,8 nck - 45 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 13.3.1 speed bin table notes absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); note : 1. the cl setting and cwl setting result in tck(avg).min and tck(avg).max requirements. when making a selection of tck(avg), bo th need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely analog - data and strobe output are synchronized by the dll - all possi ble intermediate frequencies may not be guar- anteed. an application should use the next smaller jedec standard tck(avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [ns] / tck(avg) [ns], rounding up to the next "supportedcl". 3. tck(avg).max limits: calculate tck(avg) = taa.max / cl selected and round the resulting tck(avg) down to the next valid spee d bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to cl selected. 4. "reserved" settings are not allowed. user must program a different value. 5. "optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. r efer to supplier?s data sheet and/or the dimm spd information if and how this setting is supported. 6. any ddr3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 7. any ddr3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 8. any ddr3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to production tests but verified by design/ characterization. 9. for devices supporting optional downshift to cl=7 and cl=9, taa/trcd/trp min must be 13.125 ns or lower. spd settings must b e programmed to match. for example, ddr3-1333(cl9) devices supporting downshift to ddr3-1066(cl7) should program 13.125 ns in spd bytes for taamin (byte 16), trcdm in (byte 18), and trpmin (byte 20). ddr3-1600(cl11) devices supporting downshift to ddr3-1333(cl9) or ddr3-1066(cl7) should program 13.125 ns in spd bytes for taamin (byte16), trcdmin (byte 18), and trpmin (byte 20). once trp (byte 20) is programmed to 13.125ns, trcmin (byte 21,23) also should be programmed accordin gly. for example, 49.125ns (trasmin + trpmin=36ns+13.125ns) for ddr3-1333(cl9) and 48.125ns (trasmin+trpmin=35ns+13.125ns) for ddr3-1600(cl11). - 46 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 14. timing parameters by speed grade [ table 47 ] timing parameters by speed bin speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units note parameter symbol min max min max min max min max clock timing minimum clock cycle time (dll off mode) tck(dll_of f) 8 - 8 - 8 - 8 - ns 6 average clock period tck(avg) see speed bins table ps clock period tck(abs) tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max tck(avg)min + tjit(per)min tck(avg)max + tjit(per)max ps average high pulse width tch(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) average low pulse width tcl(avg) 0.47 0.53 0.47 0.53 0.47 0.53 0.47 0.53 tck(avg) clock period jitter tjit(per) -100 100 -90 90 -80 80 -70 70 ps clock period jitter during dll locking period tjit(per, lck) -90 90 -80 80 -70 70 -60 60 ps cycle to cycle period jitter tjit(cc) 200 180 160 140 ps cycle to cycle period jitter during dll locking period tjit(cc, lck) 180 160 140 120 ps cumulative error across 2 cycles terr(2per) - 147 147 - 132 132 - 118 118 -103 103 ps cumulative error across 3 cycles terr(3per) - 175 175 - 157 157 - 140 140 -122 122 ps cumulative error across 4 cycles terr(4per) - 194 194 - 175 175 - 155 155 -136 136 ps cumulative error across 5 cycles terr(5per) - 209 209 - 188 188 - 168 168 -147 147 ps cumulative error across 6 cycles terr(6per) - 222 222 - 200 200 - 177 177 -155 155 ps cumulative error across 7 cycles terr(7per) - 232 232 - 209 209 - 186 186 -163 163 ps cumulative error across 8 cycles terr(8per) - 241 241 - 217 217 - 193 193 -169 169 ps cumulative error across 9 cycles terr(9per) - 249 249 - 224 224 - 200 200 -175 175 ps cumulative error across 10 cycles terr(10per) - 257 257 - 231 231 - 205 205 -180 180 ps cumulative error across 11 cycles terr(11per) - 263 263 - 237 237 - 210 210 -184 184 ps cumulative error across 12 cycles terr(12per) - 269 269 - 242 242 - 215 215 -188 188 ps cumulative error across n = 13, 14 ... 49, 50 cycles terr(nper) terr(nper)min = (1 + 0.68ln(n))*tjit(per)min terr(nper)max = (1 = 0.68ln(n))*tjit(per)max ps 24 absolute clock high pulse width tch(abs) 0.43 - 0.43 - 0.43 - 0.43 - tck(avg) 25 absolute clock low pulse width tcl(abs) 0.43 - 0.43 - 0.43 - 0.43 - tck(avg) 26 data timing dqs,dqs to dq skew, per group, per access tdqsq - 200 - 150 - 125 - 100 ps 13 dq output hold time from dqs, dqs tqh 0.38 - 0.38 - 0.38 - 0.38 - tck(avg) 13, g dq low-impedance time from ck, ck tlz(dq) -800 400 -600 300 -500 250 -450 225 ps 13,14, f dq high-impedance time from ck, ck thz(dq) - 400 - 300 - 250 - 225 ps 13,14, f data setup time to dqs, dqs referenced to v ih (ac)v il (ac) levels tds(base) 75 - 25 - 30 - 10 ps d, 17 data hold time to dqs, dqs referenced to v ih (ac)v il (ac) levels tdh(base) 150 - 100 - 65 - 45 ps d, 17 dq and dm input pulse width for each input tdipw 600 - 490 - 400 - 360 ps 28 data strobe timing dqs, dqs differential read preamble trpre 0.9 note 19 0.9 note 19 0.9 note 19 0.9 note 19 tck 13, 19, g dqs, dqs differential read postamble trpst 0.3 note 11 0.3 note 11 0.3 note 11 0.3 note 11 tck 11, 13, b dqs, dqs differential output high time tqsh 0.38 - 0.38 - 0.4 - 0.4 - tck(avg) 13, g dqs, dqs differential output low time tqsl 0.38 - 0.38 - 0.4 - 0.4 - tck(avg) 13, g dqs, dqs differential write preamble twpre 0.9 - 0.9 - 0.9 - 0.9 - tck dqs, dqs differential write postamble twpst 0.3 - 0.3 - 0.3 - 0.3 - tck dqs, dqs rising edge output access time from rising ck, ck tdqsck -400 400 -300 300 -255 255 -225 225 ps 13,f dqs, dqs low-impedance time (referenced from rl-1) tlz(dqs) -800 400 -600 300 -500 250 -450 225 ps 13,14,f dqs, dqs high-impedance time (referenced from rl+bl/2) thz(dqs) - 400 - 300 - 250 - 225 ps 12,13,14 dqs, dqs differential input low pulse width tdqsl 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck 29, 31 dqs, dqs differential input high pulse width tdqsh 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tck 30, 31 dqs, dqs rising edge to ck, ck rising edge tdqss -0.25 0.25 -0.25 0.25 -0.25 0.25 -0.27 0.27 tck(avg) c dqs,dqs falling edge setup time to ck, ck rising edge tdss 0.2 - 0.2 - 0.2 - 0.18 - tck(avg) c, 32 dqs,dqs falling edge hold time to ck, ck rising edge tdsh 0.2 - 0.2 - 0.2 - 0.18 - tck(avg) c, 32 - 47 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 47 ] timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units note parameter symbol min max min max min max min max command and address timing dll locking time tdllk 512 - 512 - 512 - 512 - nck internal read command to precharge command delay trtp max (4nck,7.5ns ) - max (4nck,7.5ns) - max (4nck,7.5ns) - max (4nck,7.5ns) - e delay from start of internal write transaction to internal read command twtr max (4nck,7.5ns ) - max (4nck,7.5ns) - max (4nck,7.5ns) - max (4nck,7.5ns) - e,18 write recovery time twr 15 - 15 - 15 - 15 - ns e mode register set command cycle time tmrd 4 - 4 - 4 - 4 - nck mode register set command update delay tmod max (12nck,15n s) - max (12nck,15ns ) - max (12nck,15ns ) - max (12nck,15ns) - cas# to cas# command delay tccd 4 - 4 - 4 - 4 - nck auto precharge write recovery + precharge time tdal(min) wr + roundup (trp / tck(avg)) nck multi-purpose register recovery time tmprr 1 - 1 - 1 - 1 - nck 22 active to precharge command period tras see ?speed bins and cl, trcd, trp, trc and tras for corresponding bin? on page 42 ns e active to active command period for 1kb page size trrd max (4nck,10ns) - max (4nck,7.5ns) - max (4nck,6ns) - max (4nck,6ns) - e active to active command period for 2kb page size trrd max (4nck,10ns) - max (4nck,10ns) - max (4nck,7.5ns) - max (4nck,7.5ns) - e four activate window for 1kb page size tfaw 40 - 37.5 - 30 - 30 - ns e four activate window for 2kb page size tfaw 50 - 50 - 45 - 40 - ns e command and address setup time to ck, ck referenced to v ih (ac) / v il (ac) levels tis(base) 200 - 125 - 65 - 45 - ps b,16 command and address hold time from ck, ck refer- enced to v ih (ac) / v il (ac) levels tih(base) 275 - 200 - 140 - 120 - ps b,16 command and address setup time to ck, ck referenced to v ih (ac) / v il (ac) levels tis(base) ac150 200 + 150 - 125 + 150 - 65+125 - 45+125 - ps b,16,27 control & address input pulse width for each input tipw 900 - 780 - 620 - 560 - ps 28 calibration timing power-up and reset calibration time tzqiniti 512 - 512 - 512 - 512 - nck normal operation full calibration time tzqoper 256 - 256 - 256 - 256 - nck normal operation short calibration time tzqcs 64 - 64 - 64 - 64 - nck 23 reset timing exit reset from cke high to a valid command txpr max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - max(5nck, trfc + 10ns) - self refresh timing exit self refresh to commands not requiring a locked dll txs max(5nck,t rfc + 10ns) - max(5nck,tr fc + 10ns) - max(5nck,tr fc + 10ns) - max(5nck,tr fc + 10ns) - exit self refresh to commands requiring a locked dll txsdll tdllk(min) - tdllk(min) - tdllk(min) - tdllk(min) - nck minimum cke low width for self refresh entry to exit tim- ing tckesr tcke(min) + 1tck - tcke(min) + 1tck - tcke(min) + 1tck - tcke(min) + 1tck - valid clock requirement after self refresh entry (sre) or power-down entry (pde) tcksre max(5nck, 10ns) - max(5nck, 10ns) - max(5nck, 10ns) - max(5nck, 10ns) - valid clock requirement before self refresh exit (srx) or power-down exit (pdx) or reset exit tcksrx max(5nck, 10ns) - max(5nck, 10ns) - max(5nck, 10ns) - max(5nck, 10ns) - - 48 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 47 ] timing parameters by speed bin (cont.) speed ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 units note parameter symbol min max min max min max min max power down timing exit power down with dll on to any valid com- mand;exit precharge power down with dll frozen to commands not requiring a locked dll txp max (3nck, 7.5ns) - max (3nck, 7.5ns) - max (3nck,6ns) - max (3nck,6ns) - exit precharge power down with dll frozen to com- mands requiring a locked dll txpdll max (10nck, 24ns) - max (10nck, 24ns) - max (10nck, 24ns) - max (10nck, 24ns) - 2 cke minimum pulse width tcke max (3nck, 7.5ns) - max (3nck, 5.625ns) - max (3nck, 5.625ns) - max (3nck,5ns) - command pass disable delay tcpded 1 - 1 - 1 - 1 - nck power down entry to exit timing tpd tcke(min) 9*trefi tcke(min) 9*trefi tcke(min) 9*trefi tcke(min) 9*trefi tck 15 timing of act command to power down entry tactpden 1 - 1 - 1 - 1 - nck 20 timing of pre command to power down entry tprpden 1 - 1 - 1 - 1 - nck 20 timing of rd/rda command to power down entry trdpden rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - rl + 4 +1 - timing of wr command to power down entry (bl8otf, bl8mrs, bl4otf) twrpden wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - wl + 4 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bl8otf, bl8mrs, bl4otf) twrapden wl + 4 +wr +1 - wl + 4 +wr +1 - wl + 4 +wr +1 - wl + 4 +wr +1 - nck 10 timing of wr command to power down entry (bl4mrs) twrpden wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - wl + 2 +(twr/ tck(avg)) - nck 9 timing of wra command to power down entry (bl4mrs) twrapden wl +2 +wr +1 - wl +2 +wr +1 - wl +2 +wr +1 - wl +2 +wr +1 - nck 10 timing of ref command to power down entry trefpden 1 - 1 - 1 - 1 - 20,21 timing of mrs command to power down entry tmrspden tmod(min) - tmod(min) - tmod(min) - tmod(min) - odt timing odt high time without write command or with write command and bc4 odth4 4 - 4 - 4 - 4 - nck odt high time with write command and bl8 odth8 6 - 6 - 6 - 6 - nck asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 2 8.5 2 8.5 2 8.5 2 8.5 ns asynchronous rtt turn-off delay (power-down with dll frozen) taofpd 2 8.5 2 8.5 2 8.5 2 8.5 ns rtt turn-on taon -400 400 -300 300 -250 250 -225 225 ps 7,f rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg ) 8,f rtt dynamic change skew tadc 0.3 0.7 0.3 0.7 0.3 0.7 0.3 0.7 tck(avg ) f write leveling timing first dqs pulse rising edge after tdqss margining mode is programmed twlmrd 40 - 40 - 40 - 40 - tck 3 dqs/dqs delay after tdqs margining mode is pro- grammed twldqsen 25 - 25 - 25 - 25 - tck 3 write leveling setup time from rising ck, ck crossing to rising dqs, dqs crossing twls 325 - 245 - 195 - 165 - ps write leveling hold time from rising dqs, dqs crossing to rising ck, ck crossing twlh 325 - 245 - 195 - 165 - ps write leveling output delay twlo 0 9 0 9 0 9 0 7.5 ns write leveling output error twloe 0 2 0 2 0 2 0 2 ns - 49 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 14.1 jitter notes specific note a unit ?tck(avg)? represents the actual tck(avg) of the input cl ock under operation. unit ?nck? represents one clock cycle of the input clock, counting the actual clock edges .ex) tmrd = 4 [nck] means; if one mode register set command is registered at tm, another mode register set command may be registered at tm +4, even if (tm+4 - tm) is 4 x tck(avg) + terr(4per),min. specific note b these parameters are measured from a command/address signal (cke, cs , ras , cas , we , odt, ba0, a0, a1, etc.) transition edge to its respective clock signal (ck/ck ) crossing. the spec values are not affect ed by the amount of clock jitter applied (i.e. tjit(per), tjit(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. t hat is, these parameters should be met whether clock jitter is present or not. specific note c these parameters are measured from a data strobe signal (dqs(l/u), dqs (l/u)) crossing to its resp ective clock signal (ck, ck ) crossing. the spec values are not affected by the amount of cl ock jitter applied (i.e. tjit(per), tjit(cc), etc.), as these are relative to the clock signal crossing. that is , these parameters should be met whether clock jitter is present or not. specific note d these parameters are measured from a data signal (dm(l/u), dq (l/u)0, dq(l/u)1, etc.) transition edge to its respective data strobe signal (dqs(l/u), dqs (l/u)) crossing. specific note e for these parameters, the ddr3 sdram device supports tnparam [nck] = ru{ tparam [ns] / tck(avg) [ns] }, which is in clock cycles, assuming all input cloc k jitter specifications are sati sfied. for example, the device will support tnrp = ru{trp / tck( avg)}, which is in clock cycles, if all input clock jitter specificat ions are met. this means: for ddr3-800 6-6-6, of which trp = 15ns , the device will support tnrp = ru{trp / tck(avg)} = 6, as long as the input clock jitter specifications are met, i.e. precharge com - mand at tm and active command at tm+6 is valid even if (tm+6 - tm) is less than 15ns due to input clock jitter. specific note f when the device is operated with input clock jitter, this parameter needs to be derated by the actual terr(mper),act of the inp ut clock, where 2 <= m <= 12. (output deratings are relative to the sdram input clock.) for example, if the measured jitter into a ddr3-800 sdra m has terr(mper),act,min = - 172 ps and terr(mper),act,max = + 193 ps, then tdqsck,min(derated) = tdqsck,min - terr(mper ),act,max = - 400 ps - 193 ps = - 593 ps and tdqsck,max(der- ated) = tdqsck,max - terr(mper),act,min = 400 ps + 172 ps = + 572 ps. similarly, tlz(dq) for ddr3-800 derates to tlz(dq),min(derated) = - 800 ps - 193 ps = - 993 ps and tlz(dq),max(derated) = 400 ps + 172 ps = + 572 ps. (caution on the min/max usage!) note that terr(mper),act,min is the minimum measured value of terr(nper) where 2 <= n <= 12, and terr(mper),act,max is the maximum meas ured value of terr(nper) where 2 <= n <= 12. specific note g when the device is operated with i nput clock jitter, this parameter needs to be der ated by the actual tjit(per),act of the inpu t clock. (output deratings are relative to the sdram input cloc k.) for example, if the measur ed jitter into a ddr3-800 sdram has tck(avg),act = 2500 ps, tjit(per),act,min = - 72 ps and tjit( per),act,max = + 93 ps, then trpre,min(derated) = trpre,min + tjit(per),act,min = 0.9 x tck(avg),act + tjit(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. similarly, tqh,min(derated) = tqh,min + tjit(per),act,min = 0.38 x tck(av g),act + tjit(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (caution on the min/ max usage!) - 50 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 14.2 timing parameter notes 1. actual value dependant upon measurement level definitions which are tbd. 2. commands requiring a locked dll are: read (and rap) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register 5. value must be rounded-up to next higher integer value 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. for definition of rtt turn-on time taon see "device operation & timing diagram datasheet" 8. for definition of rtt turn-off time taof see "device operation & timing diagram datasheet". 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr / tck to the next integer. 10. wr in clock cycles as programmed in mr0 11. the maximum read postamble is bound by tdqsck(min) plus tqsh(min) on the left side and thz(dqs)max on the right side. see " device operation & timing diagram datasheet. 12. output timing deratings are relative to the sdram input clock. when the device is operated with input clock jitter, this pa rameter needs to be derated by tbd 13. value is only valid for ron34 14. single ended signal parameter. refer to chapter 8 and chapter 9 for definition and measurement method. 15. trefi depends on t oper 16. tis(base) and tih(base) values are for 1v/ns cmd/add single-ended slew rate and 2v/ns ck, ck differential slew rate, note for dq and dm signals, v ref (dc) = v ref dq(dc). for input only pins except reset, v ref (dc)=v ref ca(dc). see ?$paratext>? on page 51. . 17. tds(base) and tdh(base) values are for 1v/ns dq single-ended slew rate and 2v/ns dqs, dqs differential slew rate. note for dq and dm signals, v ref (dc)= v ref dq(dc). for input only pins except reset , v ref (dc)=v ref ca(dc). see ?$paratext>? on page 57. 18. start of internal write transaction is defined as follows ; for bl8 (fixed by mrs and on-the-fly) : rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly) : rising clock edge 4 clock cycles after wl for bc4 (fixed by mrs) : rising clock edge 2 clock cycles after wl 19. the maximum read preamble is bound by tlzdqs(min) on the left side and tdqsck(max) on the right side. see "device operation & timing diagram datasheet" 20. cke is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in pro gress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low after a refresh command once trefpden(min) is satisfied, there are cases where additional time such as txpdll(min) is also required. see "device operation & timing diagram datasheet". 22. defined between end of mpr read burst and mrs which reloads mpr or disables mpr function. 23. one zqcs command can effectively correct a minimum of 0.5 % (zqcorrection) of ron and rtt impedance error within 64 nck for all speed bins assuming the maximum sensitivities specified in the ?output driver voltage and temperature sensitivity? and ?odt voltage and temperature sensitivity? tables. the appropriate interval between zqcs commands can be determined from these tables and other application specific parameters. one method for calculating the interval between zqcs commands, given the temperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is sub- ject to in the application, is illustrated. the interval could be defined by the following formula: where tsens = max(drttdt, drondtm) and vsens = max(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5% / c, vsens = 0.15% / mv, tdriftrate = 1 c / sec and vdriftrate = 15 mv / sec, then the interval between zqcs commands is calcu- lated as: 24. n = from 13 cycles to 50 cycles. this row defines 38 parameters. 25. tch(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling ed ge. 26. tcl(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edg e. 27. the tis(base) ac150 specifications are adjusted from the tis(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter- nate threshold of 150 mv and another 25 ps to account for the earlier reference point [(175 mv - 150 mv) / 1 v/ns]. 28. pulse width of a input signal is defined as the width between the first crossing of v ref (dc) and the consecutive crossing of v ref (dc) 29. tdqsl describes the instantaneous differential input low pulse width on dqs-dqs , as measured from one falling edge to the next consecutive rising edge. 30. tdqsh describes the instantaneous differential input high pulse width on dqs-dqs , as measured from one rising edge to the next consecutive falling edge. 31. tdqsh, act + tdqsl, act = 1 tck, act ; with txyz, act being the actual measured value of the respective timing parameter in the application. 32. tdsh, act + tdss, act = 1 tck, act ; with txyz, act being the actual measured value of the respective timing parameter in t he application. zqcorrection (tsens x tdriftrate) + (vsens x vdriftrate) 0.5 (1.5 x 1) + (0.15 x 15) = 0.133 ~ ~ 128ms - 51 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 14.3 address/command setup, hold and derating : for all input signals the total tis (setup time) and tih (hold time ) required is calculated by adding the data sheet tis(base) and tih(base) value (see table 48) to the tis and tih derating value (see table 49) respectively. example: tis (total setup time) = tis(base) + tis setup (tis) nominal slew rate fo r a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup (tis) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max. if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value (see figure 21). if the actual signal is later t han the nominal slew rate lin e anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating val ue (see figure 23). hold (tih) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)max and the first crossing of v ref (dc). hold (tih) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of v ih (dc)min and the first crossing of v ref (dc). if the actual signal is always later than the nom inal slew rate line between shaded ?dc to v ref (dc) region?, use nominal slew rate for derating value (see figure 22). if the actual signal is earlier than the no minal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value (see figure 24). for a valid transition the input signal has to remain above/below v ih/il (ac) for some time tvac (see table 51). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input sig nal is still required to comp lete the transition and reach v ih/il (ac). for slew rates in between the values listed in table 49, the derating values may obtai ned by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization. [ table 48 ] add/cmd setup and hold base-values for 1v/ns note : 1. ac/dc referenced for 1v/ns address/command slew rate and 2 v/ns differential ck-ck slew rate 2. the tis(base)-ac150 specifications are adjusted from the ti s(base) specification by adding an additional 125ps for ddr3-800/ 1066 or 100ps for ddr3-1333/1600 of derating to accommodate for the lower alternate threshold of 150mv and another 25ps to account for the ea rlier reference point [(175mv-150mv)/1 v/ns] [ table 49 ] derating values ddr3-800/1066/1333/1600 tis/tih-ac/dc based [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tis(base) 200 125 65 45 v ih/l(ac) tih(base) 275 200 140 120 v ih/l(dc) tis(base)-ac150 200 + 150 125 + 150 65+125 45+125 v ih/l(ac) tis, tih derating [ps] ac/dc based ac175 threshold -> v ih (ac) = v ref (dc) + 175mv, v il (ac) = v ref (dc) - 175mv clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/ add slew rate v/ns 2.08850885088509658104661127412084128100 1.559345934593467427550835891689984 1.0000000881616242432344050 0.9-2-4-2-4-2-4 6 41412222030303846 0.8-6-10-6-10-6-10 2 -2 10 6 181426243440 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -46 -44 -38 -36 -30 -26 -22 -10 - 52 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 50 ] derating values ddr3-800/1066/1333/1600 tis/tih-ac/dc based - alternate ac150 threshold [ table 51 ] required time t vac above v ih (ac) {blow v il (ac)} for valid transition tis, tih derating [ps] ac/dc based alternate ac150 threshold -> v ih (ac) = v ref (dc) + 150mv, v il (ac) = v ref (dc) - 150mv clk,clk differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih cmd/ add slew rate v/ns 2.075507550755083589166997410784115100 1.550345034503458426650745882689084 1.0000000881616242432344050 0.9 0 -4 0 -4 0 -4 8 4 1612242032304046 0.8 0 -10 0 -10 0 -10 8 -2 16 6 241432244040 0.70-160-160-168 -816024832184034 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 slew rate[v/ns] t vac @175mv [ps] t vac @150mv [ps] min max min max >2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 - - 53 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 21. illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal tf tr v ref (dc) - v il (ac)max tf = v ih (ac)min - v ref (dc) tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate v ref to ac region v ref to ac region tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs - 54 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 22. illustration of nominal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss ck ck hold slew rate hold slew rate falling signal rising signal tr tf v ref (dc) - v il (dc)max tr = v ih (dc)min - v ref (dc) tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate dc to v ref region tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs - 55 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 23. illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) v ss setup slew rate setup slew rate rising signal falling signal tf tr tangent line[v ref (dc) - v il (ac)max] tf = tangent line[v ih (ac)min - v ref (dc)] tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs tvac - 56 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 24. illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock) v ss hold slew rate tf tr tangent line [ v ih (dc)min - v ref (dc) ] tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc)max ] tr = rising signal ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs - 57 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e 14.4 data setup, hold and slew rate derating : for all input signals the total tds (setup time) and tdh (hold time) required is calculated by adding the data sheet tds(base) and tdh(base) value (see table 52) to the tds and tdh (see table 55) derating value respectively. ex ample: tds (total setup time) = tds(base) + tds. setup (tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v ref (dc) and the first crossing of v ih (ac)min. setup (tds) nominal slew rate for a falling signal is def ined as the slew rate between the last crossing of v ref (dc) and the first crossing of v il (ac)max (see figure 25). if the actual signal is always earlier than the nominal slew rate line between shaded ?v ref (dc) to ac region?, use nominal slew rate for derating value. if the actual signal is later than the nomi nal slew rate line anywhere between shaded ?v ref (dc) to ac region?, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating val ue (see figure 27). hold (tdh) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of v il (dc)max and the first crossing of v ref (dc). hold (tdh) nominal slew rate for a falling signal is def ined as the slew rate between the last crossing of v ih (dc)min and the first crossing of v ref (dc) (see figure ). if the actual signal is always later than the nominal sl ew rate line between shaded ?dc level to v ref (dc) region?, use nominal slew rate for derating value. if the actual signal is earlier than the nominal slew rate line anywhere between shaded ?dc to v ref (dc) region?, the slew rate of a tangent line to the actual signal from the dc level to v ref (dc) level is used for derating value (see figure 28). for a valid transition the input signal has to remain above/below v ih/il (ac) for some time tvac (see table 56). although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached v ih/il (ac) at the time of the rising clock transition) a valid input sig nal is still required to comp lete the transition and reach v ih/il (ac). for slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. these values are typically not subj ect to production test. they are ve rified by design and characterization. [ table 52 ] data setup and hold base-values note : ac/dc referenced for 1v/ns dq-slew rate and 2 v/ns dqs slew rate) [ table 53 ] derating values ddr3-800/1066 tds/tdh - (ac175) note : 1. cell contents shaded in red are defined as ?not supported?. [ table 54 ] derating values for ddr3-800/1066/1333/1600 tds/tdh - (ac150) note : 1. cell contents shaded in red are defined as ?not supported?. [ps] ddr3-800 ddr3-1066 ddr3-1333 ddr3-1600 reference tds(base) ac175 75 25 - -v ih/l (ac) tds(base) ac150 125 75 30 10 v ih/l (ac) tdh(base) dc100 150 100 65 45 v ih/l (dc) tds, tdh derating in [ps] ac/dc based 1 dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh ddr3 - 800/ 1066 dq slew rate v/ns 2.0885088508850---------- 1.55934593459346742 - - - - - - - - 1.0000000881616- - - - - - 0.9- - -2-4-2-4 6 414122220 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7-------3-85013821182934 0.6 - - - - - - - - -1 -10 7 -2 15 8 23 24 0.5-----------11-16-2-6610 0.4-------------30-26-22-10 tds, tdh derating in [ps] ac/dc based 1 dqs,dqs differential slew rate 4.0 v/ns 3.0 v/ns 2.0 v/ns 1.8 v/ns 1.6 v/ns 1.4v/ns 1.2v/ns 1.0v/ns tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh tds tdh dq slew rate v/ns 2.0755075507550---------- 1.55034503450345842 - - - - - - - - 1.0000000881616- - - - - - 0.9- - 0 -4 0 -4 8 4 16122420 - - - - 0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 0.6--------15-1023-23183924 0.5----------14-1622-63010 0.4------------7-2615-10 - 58 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e [ table 55 ] required time t vac above v ih (ac) {blow v il (ac)} for valid transition slew rate[v/ns] t vac [ps] ddr3-800/1066 t vac [ps] ddr3-1333/1600 min max min max >2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 155 - <0.5 0 - 150 - - 59 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 25. illustration of nominal slew rate and t vac for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock). v ss ck ck tds tdh setup slew rate setup slew rate rising signal falling signal tf tr v ref (dc) - v il (ac)max tf = v ih (ac)min - v ref (dc) tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate v ref to ac region v ref to ac region tis tih tds tdh tis tih tvac tvac note :clock and strobe are drawn on a different time scale. dqs dqs - 60 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 26. illustration of nominal slew rate for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock). v ss ck ck hold slew rate hold slew rate falling signal rising signal tr tf v ref (dc) - v il (dc)max tr = v ih (dc)min - v ref (dc) tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max nominal slew rate nominal slew rate dc to v ref region tis tih tis tih dc to v ref region note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs - 61 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 27. illustration of tangent line for setup time t ds (for dq with respect to strobe) and t is (for add/cmd with respect to clock) v ss setup slew rate setup slew rate rising signal falling signal tf tr tangent line[v ref (dc) - v il (ac)max] tf = tangent line[v ih (ac)min - v ref (dc)] tr = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent v ref to ac region v ref to ac region line line nominal line nominal line ck ck tis tih tis tih tvac note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs tvac - 62 - K4B1G1646E datasheet ddr3 sdram rev. 1.4 k4b1g0846e k4b1g0446e figure 28. illustration of tangent line for hold time t dh (for dq with respect to strobe) and t ih (for add/cmd with respect to clock) v ss hold slew rate tf tr tangent line [ v ih (dc)min - v ref (dc) ] tf = v ddq v ih (ac) min v ih (dc) min v ref (dc) v il (dc) max v il (ac) max tangent tangent dc to v ref region dc to v ref region line line nominal line nominal line falling signal hold slew rate tangent line [ v ref (dc) - v il (dc)max ] tr = rising signal ck ck tis tih tis tih note :clock and strobe are drawn on a different time scale. tds tdh tds tdh dqs dqs |
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